IT Recruiter at Infinity HR Consulting Services
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SOC Verification Engineer - System Verilog and UVM (2-9 yrs)
Critical Hiring for Pune Product based Start up Organization
Experience: 2 to 8 yrs
- Passion for Verification at module level/ full chip level.
- Object Oriented Testbench development experience using SystemVerilog / OVM/UVM
- Experience on atleast one of the Simulators - Questasim / IUS / VCS
- Exposure to constraint-random testbench development and testcase writing, functional coverage and SV assertions is a must.
- Test Plan writing, Verification Env Design Documentation experience a must
- Debug skills with fast turn around and believer of Rev0 production chips.
- Experience on Ethernet based PHY's - 1G/10G/40G/100G with R/X/e PCS and K/C/T/S Media will be a big plus
- Exposure to Ethernet PHY's Auto Negotiation, Base-T related clauses will be an added advantage
- SoC Verification experience will be an added advantage
- Exposure to Gate Level Simulations required.
- Exposure to scripting based automation using Shell/Perl required.
Please send me your updated resume