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SoC/IP Verification Engineer - C++ (3-8 yrs)
- 3 - 7 years experience
- Knowledge in one or more: imaging, graphics, video, memory, multimedia and CPU domains
- Knowledge in various peripherals controllers and interfaces - UART, I2C, I2S, SPI, USB, flash memory interfaces.
- Knowledge in bus protocols - APB, AHB, AXI, and bus interconnects
- Prefer experience in SOC architecture and/or Verification Methodology and Tool development.
- Experience with test plan and test-bench development
- Experience with test development and test coverage assessment
- Experience with current verification methodologies (UVM, OVM, VMM, Specman, ...)
- Experience with assembly language. ARM assembly preferred.
- Experience using Perl or other UNIX scripting languages for flow automation.
- Experience with object oriented programming languages (C++ preferred)
- Experience with Formal equivalence checking
- Experience with setting up and running gate level simulations
Role: The Design Verification Engineer at Company Semiconductor DS India Labs will be responsible for pre-silicon verification of a high-end mobile SOC.
- Work with RTL/Logic teams to develop and execute verification plans.
- Help define and evolve our verification methodologies.
- Create and modify SOC-level, and sub-system level test benches.
- Develop new tests to improve functional/code coverage.
- Running and debugging Top level regression.
- Formal equivalence checking
- Gate level/Power simulations
- Help support post-silicon debug.
- Timely and high quality execution per our development schedule and overall design plans
- Able to write assertions (SVA) at interface level
- Must be responsible for documentation and close all open issues with design team
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