15/07 Shobhna yadav
Talent Acquisition specialist at Smartsocs solution pvt ltd

Views:187 Applications:22 Rec. Actions:Recruiter Actions:10

Smartsocs Solution - Verification Engineer - System Verilog /UVM (3-15 yrs)

Bangalore/Hyderabad Job Code: 467723

Job Description :

- Technical execution of SOC Verification projects of complex ARM based SOCs

- Test Planning, Environment Architecture, SV-UVM environments

- Expert Knowledge in SOC Verification

- Expert at Verification - Coverage Driven Test Planning, Architecting Environments, Verification Flow

- Strong knowledge in System Verilog

- Knowledge in at least one methodology, OVM, UVM, VMM or RVM

- Very Good knowledge of protocols, at least one protocol of SATA, USB, Ethernet, PCIE

- Ability and desire to learn new methodologies, languages, protocols etc. is required

Qualification & Experience : B Tech/BE/MTech/ME/MSc in Electronics

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