03/09 Apeksha Joshi
Talent Acquisition Specialist at Smart SOC Solutions

Views:500 Applications:62 Rec. Actions:Recruiter Actions:49

Smart SOC Solutions - RTL Design Engineer - ASIC (3-7 yrs)

Bangalore/Hyderabad Job Code: 487818

Job Description :

- Deep knowledge of RTL design, Lint,Spyglass,CDC

- Deep knowledge of Verilog and SystemVerilog

- Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers)

- Proven knowledge of synthesis, static timing, DFT, is a plus

- SystemC/C++, Perl or Python knowlwdge a plus.

- Hands on experience using Verilog or VHDL HDL for design

Women-friendly workplace:

Maternity and Paternity Benefits

Add a note
Something suspicious? Report this job posting.