22/07 Apeksha Joshi
Talent Acquisition Specialist at Smart SOC Solutions

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Smart SOC Solutions - RTL Design Engineer - ASIC (3-7 yrs)

Bangalore/Hyderabad Job Code: 471132

Job Description :


- Deep knowledge of RTL design, Lint,Spyglass,CDC

- Deep knowledge of Verilog and SystemVerilog

- Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers)

- Proven knowledge of synthesis, static timing, DFT, is a plus

- SystemC/C++, Perl or Python knowlwdge a plus.

- Hands on experience using Verilog or VHDL HDL for design

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