07/08 Apeksha Joshi
Talent Acquisition Specialist at Smart SOC Solutions

Views:300 Applications:14 Rec. Actions:Recruiter Actions:13

Smart SOC Solutions - Physical Design Engineer - Timing Closure/RTL/Synopsys (3-15 yrs)

Bangalore/Hyderabad Job Code: 477598

JD :


- Block Level P&R / Sub-system Level P&R/ Tile Level P&R.

- Experienced in Cadence (EDI) or Synopsys (ICC) and Mentor (Calibre) EDA Tools.

- Process node experience to be in the range of 40nm & below (i.e. 28 nm, 16 nm, 10 nm, 7nm).

- Responsible for full chip implementation of complex SoCs (RTL-to-GDSII)

- RTL2GDSII implementation (40/28nm)

- Exposure on Low Power Implementations (multi-Voltage and switchable domains)

- Prior experience handling extremely area and power sensitive designs

- Power Network Analysis and fix exposure a must

- STA-SI analysis and timing closure expertise at block level

- Traditional clock tree synthesis experience

- DRC/LVS/ANT/PERC run and fix expertise

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