17/09 Apeksha Joshi
Talent Acquisition Specialist at Smart SOC Solutions

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Smart SOC Solutions - Lead Physical Design Engineer - ASIC/GDS/RTL (6-15 yrs)

Hyderabad Job Code: 493338

RTL 2 GDSII implementation (40/28nm)

Job Requirements :


- Exposure on Low Power Implementations (multi-Voltage and switchable domains)

- Prior experience handling extremely area and power-sensitive designs

- Power Network Analysis and fix exposure a must

- STA-SI analysis and timing closure expertise at the block level

- Traditional clock tree synthesis experience

- DRC/LVS/ANT/PERC run and fix expertise

- RF integration exposure a big plus (WiFi, Bluetooth, ZigBee)

- Strong experience on Static Timing Analysis (Primetime), EM/IR-Drop/Cross-talk analysis (PT-SI, Red hawk), formal or Physical Verification (Formality, Calibre)

- Experience in complex SOC integration, Low Power and High-Speed Design and Advanced Physical Verification Techniques.

- Provide technical guidance, mentoring to physical design engineers

- Interface with front-end ASIC teams to resolve issues

Immediate joiners are most welcome.

Freshers kindly do not send your CV.

Women-friendly workplace:

Maternity and Paternity Benefits

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