Lead Recruiter - Talent Acquisition at SeviTech Systems Pvt Ltd
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SeviTech Systems - STA Engineer - Timing Closure/Physical Design (3-10 yrs)
Location : Bangalore
Experience : 3- 10 Years
Job Description :
- You will be part of a Physical Design / Timing Closure team for projects with GHz freq range and cutting edge technologies.
- You will develop timing constraints for full chip or block level and be responsible for STA signoff for a complex multi-clock, multi-voltage SoCs.
- You will be responsible for Synthesis, Timing Analysis (STA), CTS at Full Chip or block level for technology nodes of 28nm/14nm.
Desired Skills and Experience :
- B. Tech. / M. Tech. with 3 - 10 years of experience in Synthesis, STA
- Expertise in synthesis of complex SoCs at block/top level and writing timing constraints for complex designs with multiple clocks and multiple voltage domains.
- Expertise on post layout timing closure for multiple tape outs, including timing ECOs and STA signoff
- Expertise in I/O constraints developments for Industry standard protocols (e.g. DDR1/2/3, SDR, LPDDR, Flash, SPIs, Ethernet, USBHS, USBFS, JTAG, Display etc...)
- Hands-on experience of working on technology nodes like 28nm, 20nm, 14nm,10nm
- Good knowledge of EDA tools from RC, DC, PT, PTSI
- Experience in formal verification RTL-to-netlist and netlist-to-netlist with DFT constraints
- Good knowledge of VLSI process and device characteristics.
- Good understanding of deep submicron parasitic effects, crosstalk effects etc. TCL, perl scripting
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