Senior Layout Design Engineer - Mixed Signal/CMOS (4-6 yrs)
Job Description :
- Layout design, Verification, Post-layout fixes and sign-off of high performance of Analog and Mixed Signal blocks
- Should be independently handling the blocks starting from floor-planning till tapeout
- Meeting project milestone deadlines and adhere to sign-off Quality guidelines
- Expertise in debugging complex verification issues
- Understanding of hierarchical planning (top down and bottom up) and integration.
- Have good understanding of CMOS process and fabrication
- Mentor and guide the team of Design Engineers
Required Skillset :
- Deep understanding and Independent handling of various Analog and Mixed Signal blocks such as ADC, DAC, PLL, CDR, SerDes, LVDS, HDMI, PMIC, DC-DC Converters and LDOs
- Exposure to technology node from 0.18um to 10nm, 7nm CMOS/ BiCMOS Process
- Expertise in critical layout design techniques such as Matching, Signal flow, Clock Routing, Shielding, Resistance & Capacitance reduction, Bias and Power routing.
- Good debugging skills in all physical verification checks like LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC etc.
- Proficiency in using industry standard EDA tools like Cadence (Virtuoso-L, Virtuoso-XL, PVS & QRC), Mentor Graphics (Calibre & XRC)
- Knowledge of scripting languages such as Perl and Skill is a plus
- Good team player with excellent communication skills, interfacing with the circuit team
- Must have participated in multiple successful Tape-outs
- Experience in RF design is a plus