Recruiter at 121 Hiring Private Limited
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Senior DFT Engineer - Verification/ATPG (4-10 yrs)
- Senior DFT engineer with 4-5 full chip DFT implementation and verification of scan architectures, JTAG, memory BIST, ATPG.
- The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools.
- The engineer needs to have hands on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF.
- The engineer with experience on debug and root cause the problem in simulation failures.
- Self-motivation, flexibility, with strong inter-personal skills. Effective communication skills, oral and written skills.