19/12 Prashant Jagad
Founder at The HRism

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Senior Design Verification Engineer - Verilog/system Verilog (4-10 yrs)

Ahmedabad/Pune Job Code: 392015

Responsibilities :


- Understand the standards/specifications

- Architecture development and documenting implementation level details

- Hands on work for every aspect of verification cycle

- Responsible for the compliance with the latest Methodologies

- Define Functional Coverage matrix and Comprehensive Test plan

- Regression management and functional coverage closure

- DUT integration and verification for IP delivery sign-off

Required Skills & Experience :

- 5+ years of experience in the relevant field

- Hands-on experience of complete verification cycle with strong verification concepts

- Verilog, SystemVerilog and UVM expertise

- Experience in any Processor based system, SoC, AMBA System bus and DMA concepts

- Hands on work experience on any of DDR/PCIe/Eth/USB/SATA/DP/HDMI/MIPI etc.

- Scripting for automation, release process, simulations, regressions

- Good command over written and oral communication

Desirable Skills & Experience :

- Lead the DUT-verification phase with 2 or more junior engineers

- Experience in FPGA based pre-silicon verification

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