HR at Samsung India Electronics
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Samsung India Electronics - RTL Design Engineer - ASIC/MATLAB (2-9 yrs)
Title : RTL Designer
Location : Bangalore
Salary : As per the company standard
General Description :
- Design and development of digital HW modules (on FPGA/ASIC using Verilog)
- Responsible for designing, modeling, verifying and integrating the digital sub-systems implemented on the state of art FPGAs/ASICs.
Areas of interest are (one of them) :
a) RTL design for digital signal processing logic design (in Verilog), like filter, fft, matrix operations, control, etc.
b) FPGA, Ethernet packet processing (hardware acceleration), (de-)packetizing modem data for e-CPRI
c) RTL design for SERDES interfaces - FPGA systems - Project deliverables include RTL code/models/algorithms of digital modem sub-systems on FPGA/ASICs; these models are to be (a) bit-accurate matches to the corresponding MATLAB/C/other implementation, (b) meeting very strict timing requirements and (c) are to be used for link-level performance characterization and field trials with RF.
- Apply critical problem solving skills of complex modem subsystems including PHY, RF, and lower stack implementation.
Necessary Skills / Attributes :
- BS/BE/B.Tech n ECE or CSE with 4-8 years of experience or Masters of Engineering degree in ECE or CSE with 3-6 years of experience in one of them
- DSP-VLSI digital systems design for 3G/4G/5G wireless modems
- High-speed interfaces (10G, 40G, JESD, packet accelerators for 10G)
- RTL design for SERDES interfaces (e.g., working with raw SERDES) - have demonstrated technical leadership and a strong modem digital HW system design background is preferred.
- Hands on experience with design, verification, and debug of gigabit rate baseband wireless modems coded in RTL (VHDL/Verilog) and targeted for FPGA and/or ASIC, including debug in RTL simulation or lab environment.
- Must possess strong organizational, interpersonal, and communication skills
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