28/03 Vijayasekaran R
Manager HR at Riconz Technologies

Views:301 Applications:44 Rec. Actions:Recruiter Actions:31

RTL Verification Engineer - VLSI Design (2-5 yrs)

Bangalore/Hyderabad/Noida Job Code: 311291

JD for RTL Verification:

Location : Bangalore/Noida/Hyderabad

Exp : 1.5-5 yrs

Engineering process and methodologies. Exposure to the complete lifecycle of ASIC Flow is essential.


- Interface with the engineering team to gather requirements. Improves process and tools methodologies (as needed).creates requirement documents/SOW for the development team communicates effectively with the stakeholders.


- Ability to prioritize, plan, coordinate and deliver on multiple tasks/projects simultaneously.


- Ability to adjust and set priorities to meet deadlines. Proficient in hands on SOC Design methodologies.


- Create manage and track project deliverables including but not limited to:

Job Description :

- Frontend design/verification

- Directed processor based (assembly/C) based verification

- Exposure Arm processors

- APB/AHB/AXI protocol understanding

- Understanding & exposure to SoC verification env and standard peripheral knowledge.

- Code coverage analysis and closure

- Behavioral model & Test bench development

- Random verification (Added advantage)

- System Verilog coding

- BFM/Scoreboard development

- VMM/OVM/UVM methodology understanding

- Functional coverage driven verification

- Working with Standard tools NCSIM, VCS

- Gate level simulation/debug

- Scripting language exposure

Minimum Experience :

- 2+ years with demonstrated experience in project management in VLSI Design Flow.


- Possesses sufficient technical competency to participate in and add value to program and technical discussions and resolving issues.

- Excellent verbal and written communications skills.


- Excellent team interface skills and the ability to work under tight timelines excellent analytical skills good understanding of technical knowledge, engineering language, and acronyms must function self-sufficiently with little direct supervision

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