31/07 Shehanaaz
Senior Talent Acquicition at BHRS

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RTL Verification Engineer - System Verilog/C (3-10 yrs)

Bangalore Job Code: 474770

Job Description :


Job Title : Design Verification

- Experience with SV/UVM/OVM/VMM or Specman/eRM/UVMe

- Experience with SOC with C/ASM based tests, Graphics or CPU is an added advantage

- SOC - System on Chip Verification; lot of IP's (100 - .)


- Proficient on protocols - AXI, AHB, USB, PCIe, DDR, LPDDR, HDMI, MIPI, Ethernet.

- Should have good understanding of Digital Design Flow (CDC, Low Power, HDL Simulation, Synthesis) & Tools

- Preferred to have know-how of ARM Cortex-A series Cores like A7; AMBA Busses - AXI, AHB, ATB, APB and Associated Peripheral / Debug components.

- Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC

- System Verilog - Language like C

- UVM - methodology

- Specman e Language - language like Verilog similar to SV

- Methodology used is eRM

- Everyone is migrating to SV

- ARM based processor on above lot of IP configured, 5 - 10 ARM core, IP's like PCI, USV, Ethernet, SPI, Sadus, Memory controllers, DDR, I2C

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