IT Recruiter at Infinity HR Consulting Services
Views:404 Applications:29 Rec. Actions:Recruiter Actions:13
RTL Synthesis Engineer - EDA/Design Verification (7-12 yrs)
Job Description :
- Design verification at RTL level is critical for time to market and various innovative ways are needed for faster verification. Emulation based verification had been grown significantly over years due to increase in design size and various verification complexity in all domain being functional validation, power verification/estimation and most important performance.
- Extended verification complexity is needed to do shift left in verification area. Performance plays a significant role in emulation based validation to make sure design verification is done in time.
- Emulation platform Veloce leads solving above challenges in all domains.
- The person in this role will be responsible for leading, developing, enhancing and maintaining key components of the RTL Compiler (frontend RTL Synthesis of Veloce) domain.
- The candidate should have experience in EDA software, preferably in the RTL synthesis domain.
1. B.Tech or M.Tech in CSE/EE/ECE from a reputed engineering college like the I.I.Ts.
2. 8 to 12 years of relevant experience in EDA tool development. Experience with RTL synthesis tools is a plus
3. Should have advanced knowledge of C/C++, data structures and algorithms.
4. Should have working knowledge and concepts of synthesis related flow especially in RTL level optimizations and technology mapping.
5. Should have worked on large software projects and be familiar with software development processes.
6. Should have prior experience of optimizing and enhancing software code for performance and memory.
7. Working knowledge of HDL languages like Verilog/SV/VHDL is plus.
8. Should be able to communicate well in English, both verbal and written.
9. Self-motivated individual and willing to lead motivated team technically.
1. Develop key software components with high quality results on RTL synthesis.
2. Work on various RTL Synthesis optimizations, technology mapping flow and also on timing driven synthesis.
3. Independently test, benchmark and fix issues in synthesis.
4. Identify and work on potential improvements and optimizations.
5. Extend and maintain the functionality of the RTL Compiler as needed.
6. Write technical specs and participate in technical discussions, code reviews.
7. Lead the team to jointly solve technical problems and within given deadline.