03/05 Murali
Manager at BHRS Consulting

Views:261 Applications:26 Rec. Actions:Recruiter Actions:9

RTL/SOC Verification Engineer - System Verilog (3-8 yrs)

Bangalore/Chennai/Hyderabad/Noida Job Code: 439993

Job Description :

- Good in programming: System Verilog, PERL/Shell script

- OVM/UVM Methodology knowledge and experience

- Excellent hands-on debug skills and problem-solving attitude

- Must have good knowledge on the verification flows

- Experience of working in complex test-bench/model in Verilog, System Verilog (SV)

- Experience of working on Functional Verification, SoC Verification

- Scope of projects: Interface IP subsystems usually including one or more controllers, one or more PHYs, custom logic usually developed by Synopsys, glue logic

- Protocols: DDR, USB, PCIE, Ethernet, HDMI, DisplayPort, MIPI CSI and DSI

- Expertise: UVM test bench development, test case development, verification plan development, debug

Women-friendly workplace:

Maternity and Paternity Benefits

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