RTL Designer - Verilog/System Verilog (4-10 yrs)
- Good understanding of frontend design methodology, RTL design, Simulation, Synthesis and Static Checks ( Lint, CDC & Low Power) and over all IP Quality.
- Good expertise in HDL (Verilog/System Verilog, VHDL), Scripting (Python, Perl & TCL), MYQSL/MongoDB, C/C++, PHP,
- Good hands on experience on software coding practices and methodology.
Experience - 4 + years.