04/07 Dinesh
HR at Magna Infotech

Views:184 Applications:23 Rec. Actions:Recruiter Actions:0

RTL Designer - Verilog/System Verilog (4-10 yrs)

Bangalore Job Code: 463870


- Good understanding of frontend design methodology, RTL design, Simulation, Synthesis and Static Checks ( Lint, CDC & Low Power) and over all IP Quality.

- Good expertise in HDL (Verilog/System Verilog, VHDL), Scripting (Python, Perl & TCL), MYQSL/MongoDB, C/C++, PHP,

- Good hands on experience on software coding practices and methodology.

- Knowledge of version control system like Git/Perforce and web development languages like Javascript, NodeJS, CSS, REST, JSON, XML and YAML would be a big plus.

Experience - 4 + years.

Women-friendly workplace:

Maternity and Paternity Benefits

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