04/06 Sivadeepa Ch
HR Recruiter at Visionyle Solutions Pvt. Ltd.

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RTL Designer - Embedded Protocols (5-10 yrs)

Bangalore/Hyderabad Job Code: 451640

Job Description Details :

- Responsibilities include RTL development, Micro Architecture Level design, STA (synthesis and timing closure (ASIC/FPGA)

- Hands-on experience with Writing timing constraints, Lint, CDC Analysis, GLS ( Gate level Simulation)

- preferable to hands-on experience with Bus protocol's AMBA AHB, APB, AMBA AXI, OCP

- preferable to hands-on experience with Key protocol's MIPI/WIFI/Ethernet/PCIe/USB/Multimedia/UFS/ARM CPU/DDR3/DDR emulation.

- Experience in real time debugging of Xilinx Chip scope Pro and Logic Analyzer, Validation

- Modeling Language : Verilog HDL, VHDL, System Verilog

- Scripting language: Perl, TCL

- Preferable to hands-on experience with Synthesis tools: DC (Design compiler), RC (RTL Compiler)

- Preferable to hands-on experience with CDC & lint Analysis tools: 0in tool, Spyglass

- Operating System: Windows, Linux, Unix

- Preferable to hands-on experience with Design tools Cadence NC-Sim, ModelSim, Questa 10.0a., FPGA Tools Xilinx ISE, Altera Quartus II, Microsemi, Vivado, etc-

Women-friendly workplace:

Maternity and Paternity Benefits

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