Recruitment Head at FresherMart
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RTL Design/Verification Engineer - ASIC/DFT/System Verilog (5-8 yrs)
- RTL Design Engineer (Experience: 5+ Years, Location: Noida)
- The candidate should have 5-7 Yrs Experience in FE Design .
- RTL development of complex blocks, Design partitioning based on given specifications.
- Strong digital design fundamentals, ASIC digital design flow.
- Know how of timing constraints development, synthesis flow, Formal Verification, DFT.
- Lint/CDC/RDC using Spyglass or any other tool.
- Scripting TCL/PERL.
- Exposure to High speed interface protocols (PCIe, USB, SATA, Ethernet) will be added plus.
RTL Verification Engineer
(Experience: 5+ Years, Location: Noida)
- Must possess B. Tech/M. Tech in Electronics and Communications with 5+ years of experience with functional verification
- Must have very good understanding of Digital Design and digital functional verification;
- Should be conversant with scripting;
- Very Good hands on with RTL/debugging experience with RTL (Verilog/VHDL), Advanced know-how of System Verilog
- Strong on debugging skills of complex designs
- Shall create test plans, coverage targets w.r.t. functional specification
- Hands on with one/more verification methodologies (UVM/OVM/VMM), Shell/Perl Scripting.
- Experience with High Speed Serial interfaces verification (USB 3.1/PCIe/)
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