03/07 Ramakrishna
Recruitment Consultant at Travash Software Solutions Pvt Ltd

Views:74 Applications:8 Rec. Actions:Recruiter Actions:1

RTL Design Engineer - Verilog/System Verilog (7-16 yrs)

Hyderabad Job Code: 463160

RTL Design Engineer

Work Location: Hyderabad

Relevant Experience: 8-15 years

Job Description :

- RTL design and micro-architecture

- Knowledge of Verilog/systemVerilog

- To be able to verify own design code with a test-bench designed by himself/herself

- Knowledge of RTL audit tools - Lint/CDC

- Formal verification - LEC

- Concepts of static timing analysis

- Should be able to write timing constraints

- Scan insertion skill is good to have, not mandatory

- Scripting skill is definite plus - perl etc

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