Sr. technical Recruiter at eTeam Info Services Pvt Ltd
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RTL Design Engineer - Verilog/system Verilog (3-10 yrs)
We have an urgent requirement for One of the Product bases MNC sarjapua,
Please find the below Job Description.
- Good understanding of frontend design methodology, RTL design, Simulation, Synthesis and Static Checks ( Lint, CDC & Low Power) and over all IP Quality.
- Good expertise in HDL (Verilog/System Verilog, VHDL), Scripting (Python, Perl & TCL), MYQSL/MongoDB, C/C++, PHP,
- Good hands on experience in software coding practices and methodology.
Experience - 4 + years.