25/07 Tulsi Arora
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RTL Design Engineer - Verilog/System Verilog (2-9 yrs)

Bangalore Job Code: 472506

Our MNC client is a leading semiconductor company designing IC products in High-Performance Timing (Clocking), RF and Power Management area.

They are looking for RTL Design to be based at Bangalore with the following :

- Total 2 to 9 years of experience in working with both front-end and back-end digital design teams.

- Must have expertise in module architecture and specification, mixed-signal centric digital design SOC.

- Must have experience in development of RTL using Verilog/System Verilog and doing block-level testing before hand-off to verification.

- Synthesis of RTL and doing quality analysis of netlist - clock gating, power, gate count analysis, gate-level simulations, LEC.

- Must have worked with verification team in helping develop and review test plan for blocks and full device.

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