31/07 Surekha
HR Recruiter at Visionyle Solutions

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RTL Design Engineer - System Verilog/Microprocessor (2-7 yrs)

Bangalore Job Code: 474762

Job Description :

- RTL design, synthesis, static timing analysis, formal verification, PLDRC, clock domain crossing, and low power techniques. Knowledge and experience of microprocessor integration is a definite advantage.

- Experience in RTL integration and Linting tools, CDC tools and UPF

- Simulation systems (e.g. Modelsim, VCS)

- Synthesis tools (e.g. Design Compile)

- Static timing tools (e.g. Prime Time)

- Code coverage, System Verilog Assertion, etc

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