01/07 Shash
CEO at Vhunt4U

Views:74 Applications:10 Rec. Actions:Recruiter Actions:3

RTL Design Engineer - SoC/ASIC (5-14 yrs)

US Job Code: 461923

JD :

- Digital RTL development of one or more IPs.

- Familiarity with state-of-art SoC design implementation.

- RTL design and verification using Verilog or System Verilog

- Synthesis and static timing analysis, physical design flow, testbench creation and simulation, some familiarity with analog/mixed-signal design and verification flows

- Need ability to understand requirements, come-up with micro architecture & implement.

- Domain of work is Serial Interfaces (SERDES & PHY) like USB/USB/MIPI/PCIe/Ethernet/JESD.

- Candidate will fully own the digital design for his IP.

- The design involves control loops between analog and digital. Candidate needs basic knowledge of control system and basics of primary electrical signals

- Supporting timing closure by providing constraints, clock tree spec, helping out on critical paths required.

- Partner with our customers in IP integration, post silicon bringup and debug, answering technical questions.

- Continuous process improvement & automation using perl/tcl or other methods is good skill to have.

- Hands on experience in Multi Clock designs, Asynchronous interface is a must.

- Experience on tools utilized in all phases of ASIC development such as Lint, CDC, Simulation etc. is required.

- Knowledge of low power concepts and experience is a plus.

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