Recruitment Operation Head at Management Consulting
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RTL ASIC Design Engineer - Verilog (2-10 yrs)
Excellent open position with Top Tier Semiconductor MNC based in Bangalore
Qualification : B.E/B.Tech or M.E/M.Tech/M.S in Electrical or Electronics
Notice : Should be willing to join in 45 days max
RTL Design: -
- Minimum of 3+ experience in RTL Logic design.
- RTL Integration experience at Subsystems/SoC
- Candidate should have Worked on RTL Lint, Lintra or Spyglass-Lint design flows
- Required Experience on CDC analysis.
- Required Experience on Febe flow (Design Compiler, fev) - For Logic handoff to Backend team
- Should have Worked on UPF, Spyglass-LP design flows
Areas of interest are (expertize in any one of them) :
- Domain (a): RTL design for digital signal processing logic design (in Verilog), like filter, fft, matrix operations, control, etc.
- Domain (b): FPGA, Ethernet packet processing (hardware acceleration), (de-) packetizing modem data for e-CPRI.
Domain (c): RTL design for SERDES interfaces - FPGA systems