RTL/ASIC Design Engineer - System Verilog (3-15 yrs)
Mandatory Keywords : (LINTING or CDC or SPYGLASS)
Job Description :
- Must have 3 to 15 years of practical experience with details of RTL development (VHDL and/or Verilog) including: functional and structural RTL design, design partitioning, simulation and regression, collaboration with design verification team.
- Must have good familiarity with latest RTL languages and tools, including: simulation systems (e.g. Modelsim, VCS), synthesis tools (e.g. Design Compile), static timing tools (e.g. Prime Time), Linting tools, CDC tools, UPF, code coverage, System Verilog Assertion, etc.
- Experience with the following area is highly desirable: Strong processor architecture knowledge Microarchitecture implementation Microprocessor integration Low power design Excellent verbal and written communication skills.
- Ability to work in a team environment.
- Good self-direction and time management skills
Preferred Qualifications :
- Develop RTL for multiple logic blocks of a DSP core Run various frontend tools to check for linting, clock domain crossing, synthesis, etc.
- Work with physical design team on design constrain and timing closure
- Work with power team on power optimization
- Work with verification team to collaborate on test plan, coverage plan, and coverage closure
Education : Bachelor's degree in Engineering, Information Systems, Computer Science, or related field.