26/11 Magnify Consultancy
Proprietor at Magnify Consultancy Services

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RTL ASIC Design Engineer - FPGA/SoC (2-8 yrs)

Bangalore Job Code: 384306

Role : RTL Design


Description :

- Minimum of 3+ experience in RTL Logic design.

- RTL Integration experience at Subsystems/SoC

- Candidate should have Worked on RTL Lint, Lintra or Spyglass-Lint design flows

- Required Experience on CDC analysis.

- Required Experience on Febe flow (Design Compiler, fev) - For Logic handoff to Backend team

- Should have Worked on UPF, Spyglass-LP design flows

Areas of interest are (expertize in any one of them) :

- Domain (a): RTL design for digital signal processing logic design (in Verilog), like filter, fft, matrix operations, control, etc.

- Domain (b): FPGA, Ethernet packet processing (hardware acceleration), (de-) packetizing modem data for e-CPRI.

Domain (c): RTL design for SERDES interfaces - FPGA systems

Qualification : B.E/B.Tech or M.E/M.Tech/M.S in Electrical or Electronics

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