Assistant Program Manager at Redpine Signals
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Redpine Signals - SoC/Chip Design Engineer - VLSI (2-5 yrs)
Role : SoC/Chip Designer
Job Description :
- The position requires strong knowledge of complex SoC/chip architectures with multi-core, multi-threaded processor subsystems, interconnects, memory architecture and caches, multiple clocks and resets, high-speed interfaces, peripherals.
- The candidate should be able to contribute to and own multiple development stages like architecture, microarchitecture, verification of SoCs which include ARM Cortex and proprietary processor designs, AMBA AHB/AXI/APB interconnects buses, high-speed interfaces for off-chip memories and be able to deliver reusable and robust IP.
- The candidate should have knowledge of SoC design flows and signoff criteria including Lint, CDC, Formal Verification, Synthesis, Constraints and STA Timing Closure.
- Knowledge of low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency scaling) is part of the minimum requirements.
Experience Level : 2- 5 years
Education Requirements : B.Tech/M.Tech in ECE, EEE or CSE
Minimum Qualifications :
- Knowledge of high-speed interfaces like USB, PCIe, Ethernet, Mobile DDR, Quad/Octa-SPI
- Knowledge of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, QEI, CAN and M4 processor.
- Knowledge of design signoff flows including Lint, CDC, Formal Verification, Synthesis, Constraints and STA Timing Closure
- Knowledge of DFT including Scan, MBIST
- Knowledge of low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency scaling)
- Knowledge of Verilog and System Verilog
- Knowledge of scripting languages like Perl, Python, Tcl, shell
Good to have : Protocols knowledge : Wi-Fi, ZB, Bluetooth