Assistant Program Manager at Redpine Signals
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Redpine Signals - ASIC Design Engineer - FPGA/SoC/Verilog (2-6 yrs)
Job Title : ASIC Design Engineer
Job Description :
- The position requires strong knowledge of complex SoC/chip architectures with multi-core, multi-threaded processor subsystems, interconnects, memory architecture and caches, multiple clocks and resets, high-speed interfaces, peripherals.
- The candidate should be able to contribute to and own multiple development stages like architecture, micro architecture, design, verification of SoCs which include ARM Cortex and proprietary processor designs, AMBA AHB/AXI/APB interconnects buses, high-speed interfaces for off-chip memories and be able to deliver reusable and robust IP.
- The candidate should have knowledge of SoC design flows and signoff criteria including Lint, CDC, Formal Verification, Synthesis, Constraints and STA Timing Closure.
- Knowledge of low power design methodology is part of the minimum requirements.
Desired profile of the candidate :
Educational Qualification : B.Tech / M.Tech in VLSI, ECE or CSE
Desired background :
- Strong in Verilog, System Verilog, C, scripting
- Areas of expertise include micro architecture, RTL Design, Digital Design and Functional Verification
- Knowledge of wireless protocols such as WLAN, ZigBee, Bluetooth, ANT
- Thorough familiarity with AHB based SoC design flow
- Experience with interfaces like SDIO/PCIe/USB/Ethernet/SPI/I2C/I2S/UART/memory controller
- Exposure to Ultra low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency scaling)
- Good Experience in integration and implementation of RTL modules.
- Experience in Logic synthesis and simulations using tools to analyze the design
- Exposure to spyglass, formality and code coverage
- Good exposure to Clock Domain Crossing Techniques and Static Timing Analysis
- Strong design skills with good visualization of data and control path
- Should have handled reasonably sized data & control path intensive blocks with independent responsibility
- Exposure to FPGA based flow. Working experience with hardware design team in board bring up. Validation experience with chipscope, Logic Analyzer and Oscilloscope
- Exposure to UVM based Testbench development, test plan and test cases creation.
Desired work experience : Min 3 years to Max 5 Years