Talent Acquisition Consultant at Quest Global
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Quest Global - VLSI Verification Engineer - UVM (5-8 yrs)
Required Skills :
- Strong verification skills, UVM methodology
- Object oriented programming, white-box/black-box, directed/random testing, coverage.
- Strong capability in building a verification environment
- Scripting Perl/ Python/Shell
- Design verification Skills
- Miscellaneous tasks in connection to the block design
- Verification planning
- Verification specification
- Verification environment (creation/adaptation/maintenance).
- Verification documentation
- Test case creation
- Usage of reference models
- Constrained random testing
- Creation of Coverage matrix
- 5-8 years of experience in verification
- Good experience in System Verilog and UVM Methodology based verification
- Excellent experience in module level & SoC level verification
- Experience in verifying ARM based designs
Brief Description of the Project/Assignment :
- The project involves development and verification of digital designs for ASICs and FPGAs using Verilog or System Verilog to meet functional and performance requirements.
Roles and Responsibilities :
- Plan & Execute end to end verification
- Define the test bench architecture for the functional blocks at the unit/sub-system/SoC level.
- Develop & own verification environment at module level as well as SoC level
- Lead a team of 4-6 verification engineers
- Capture technical requirements from Japanese customer
- Own the requirements
- Communicate to the development team in English
- Communicate directly with the customer on any technical issues and offer solutions whenever required.
- Assure the quality of the deliverables from the team before delivering to customer.
- Fulfill the customer expectations.
Min. Qualification :
- B.E/B.Tech in Electronics
Job Type (Permanent/ Contract) : Permanent
Job Location : Kanagawa, Japan
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