07/08 Shahid Mal
Senior Consultant at Adecco India

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Pysical Design Engineer - DRC/LVS/TimingClosure (4-10 yrs)

Bangalore Job Code: 478027

Job Responsibilities and Requirements :

- Independent planning and execution of Netlist-to-GDSII.

- Full exposure to all aspects of design flows like floorplanning, placement, CTS, routing, crosstalk avoidance, physical verification

- Well versed with the level timing closure (STA), timing closure methodologies, ECO generation and predictable convergence. Well versed with parasitic extraction, LVS/DRC and other Physical verification checks.

- Should be able to provide clear directions to the team wrt PNR issues Drive methodology with help of local and external CAD/EDA teams for faster design convergence

- Well aware of place and route methodologies and hands on experience with timing convergence

- 4-15 yrs experience in Physical Design Execution

- Should have good exposure to high frequency design convergence and descent exposure to physical design methodology

- Masters/Bachelors Degree in Electrical/Electronics science engineering with at least 5+ years of experience in IC design Experience in leading block level or chip level Timing closure & Physical Design activities.

- Work independently in the areas of RTL to GDSII implementation Ability to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc.

- Knowledge of low power flow (power gating, multi-Vt flow, power supply management, etc.)

- Circuit-level comprehension of time-critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM, etc.)

- TCL/Perl scripting Willing to handle technical deliveries with a small team of engineers.

- Strong problem-solving skills

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