Associate Consultant at Careernet Technologies
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Product Validation Design & Verification Engineer - Verilog/VHDL (7-11 yrs)
Looking Candidates for Top EDA firm.
- This job is for an Electrical, Electronics or Computer Science Engineer with a good understanding of HDLs (Verilog and/ or VHDL).
- He/ she should have prior experience in simulation/ emulation using these languages.
- He/ she should have a good working knowledge of EDA tools (Cadence/ Others) with focus towards debugging design/ verification problems using these tools.
- He/ she should have working knowledge of using UNIX/ Linux, utilities and shell scripts.
- Experience in automation with scripting is prefered.
- Experience with SystemVerilog is a plus.
- Experience with Functional Verification of digital systems, e.g. ASIC/SoC Verification is a strong match for this position.
Emulation : - Palladium, Zebu, Veloce
Language : - System Verilog, Verilog
Scripts : - Perl, bash, python
- Good communication and teaming skills are essential in this position.
- The person should have experience in software testing methods/ tools.
- An understanding of the Software Development Process (or a Product Development Process) is preferred.