Principle AMS Verification Engineer - Verilog/System Verilog (6-12 yrs)
- Good knowledge of system level description language skills like System Verilog, Verilog-AMS, Matlab, or SystemC.
- Good Knowledge of mixed-signal simulation CADENCE tool environment (SPECTRE, AMS Designer) and/or Questa ADMS tools
- Perform Sub-system and Chip level AMS simulations
- Good understanding of analog macros such as Buck, LDO, ADC/DAC, PLL, Oscillator, Bandgap, Comparator, etc.
- Develop Verilog, Verilog-AMS/Real models for efficient simulations.