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Principal Engineer - VHDL/Verilog (6-9 yrs)
RTL Implementation-Senior Engineer
Job Responsibilities :
- Develop and execute implementation plans to synthesize, implement Design For Test, and close timing on complex digital integrated circuits at the block, subsystem or chip level, which are coded in VHDL/Verilog.
- Use metric-driven techniques to help ensure first-pass working silicon.
- Design, implement and maintain synthesis, DFT and Static Timing scripts using best-in-class methodologies.
- Analyze log and report files to ensure the tools are getting the required results and make adjustments to the scripts to get the required results within the scheduled milestones.
- Mentor Junior team members and contractor on implementation flows and projects.
- Communicate regularly with the project teams world-wide to resolve issues, communicate status and solve technical problems.
Job Qualifications :
This position requires at least B.E/B.Tech in Electronics with 4-9 years of ASIC development experience in a fast paced environment with following experience.
- Synthesis & STA experience in high performance design (high speed / low power) is a must.
- Experience with tools and methodologies for Synthesis - hierarchical synthesis, DFT handling, retiming, clock gating, logic restructuring, optimization.
- Experience in synthesis algorithms, best RTL coding for synthesis, low-power and high-speed design trade-offs, 'physical aware' synthesis, deep sub-micron process effects.
- Experience in closing timing on block level and chip level in a highly complex clocking environment.
- Good scripting skills; knowledge of synthesis & timing algorithms.
- Backgrounds on standard cell, layout, timing/power views, and characterization would be added advantage.
- Must be able to work autonomously.
- Excellent oral and written communications skills.