25/06 Anu Kumari
Senior Specialist- People Operation at Pretlist India pvt. Ltd.

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Pretlist - FPGA/Senior FPGA Engineer - Verilog/VHDL (2-9 yrs)

Delhi NCR/Noida Job Code: 460050

Job Description for Sr. FPGA Engineer:

Pretlist powers secure mesh networks. We help businesses and governments communicate and navigate offline and without Carrier Networks.

If you are an FPGA Design Engineer with passion, then join our growing team. You will get a rare chance to craft Peer to Peer (P2P) applications that work offline. You dream it; you build it. Let's build something big together.

Key Responsibilities :

- Define and architect high-performance FPGA blocks that power our Software Defined Radios (SDR)

- Manage project priorities, deadlines, and deliverables

Minimum Requirements :

- BA, BS, or BE degree in Electrical Engineering, Computer Science, or a related field

- 2 to9 years of experience with Verilog or VHDL for Xilinx FPGAs using Vivado

- Experience with DSP flows on simulation software, such as LabView, MathWorks MATLAB, Simulink

Generous Benefits :

- You will join a global team that supports your professional dreams

- You will enjoy leave policies that promote your work-life balance

- We offer a great salary and benefits package

Pretlist does not discriminate because of age, gender identity, race, religion, or beliefs. We are proud to be an equal opportunity employer.

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