06/02 Esha Yusuf
Senior Specialist - People Operations at Pretlist

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Pretlist - FPGA Design Engineer - Verilog/System Verilog (2-6 yrs)

Noida Job Code: 408748

Company Profile :

Pretlist powers secure mesh networks. We help businesses and governments communicate and navigate offline and without Carrier Networks.

If you are an FPGA Design Engineer with passion, then join our growing team. You will get a rare chance to craft Peer to Peer (P2P) applications that work offline. You dream it; you build it. Let's build something big together.

Responsibilities :

- Define and architect high-performance FPGA blocks that power our Software Defined Radio (SDR)

- Simulate and verify logic design for maximum throughput.

Minimum Requirements :

- BA, BS, or BE degree in Electrical Engineering, Computer Science, or a related field

- 2+ years of experience with RF design using Verilog or VHDL for Xilinx FPGAs

- Experience with DSP flows on simulation software, including Vivado and MathWorks MATLAB, Simulink

Generous Benefits :

- You will join a global team that supports your professional dreams

- You will enjoy leave policies that promote your work-life balance

- We offer a great salary and benefits package

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