Senior Requirement Consultant at Resource Weaver
Views:62 Applications:4 Rec. Actions:Recruiter Actions:1
Physical Design Engineer - SoC/ASIC (6-10 yrs)
Physical Design Engineer With :
- 6 - 10 years of experience
- 3 - 6 Year of experience in Physical Design
Responsible for Constraints generation at IP level and Top Level, IP Level Synthesis, Full chip timing analysis, timing closure and support to Physical Design team.
Mandatory Skills :
1) Hands on experience in synthesis & STA and handled at least 2 to 4 complex ASIC / SOC tapeouts.
2) Expert in synthesis of complex SoCs block / top level and timing closure concepts including developing timing contrasts, validating the functional & test mode timing constraints from scratch and sign off.
3). Experience with Topographical and Power aware synthesis is must
4). Experience of low power design methodologies and high-performance designs.
5). Exposure and understanding of DFT concepts are essential.
6). Strong script programming skills including PERL and TCL.
Desired Skills :
1) In depth knowledge and hands on experience in understanding the design and developing the timing constraints both at block and SOC level, decision on timing modes and the corners.
2) Expert in design knowledge to suggest multiple types of design changes for better synthesis and timing closure
3) Experience in developing timing contrasts, validating the functional & test mode timing constraints from scratch and sign off at IP Level and Top Level
4) Experience of Synthesis environment creation and development of reference flow at module level and top level.
5) Expert in low power design methodologies and Topographical and Power-aware synthesis.
Location : Hyderabad