Physical Design Engineer - FinFET Technology (10-20 yrs)
- Assemble the full chip database for a high performance FINFET processor, verify all signoff citeria were met, and then release to the foundry.
- Actively participate in the debug of full chip assembly roadblocks such as CAD, timing, EMIR, logical and physical verification.
- Own the chip floorplan and the chip assembly methodology that enables early resolution of integration issues
- Lead and mentor junior employees and collaborate with the front end design team
- Proven ability building a hierarchical, high performance processor in FINFET technology
- Expert in developing flows to drive block PnR, Timing Closure and Final sign off.
- Solid understanding of block P&R : STA and timing closure, power/clk distribution and analysis, RC extraction and correlation, SI analysis, resolving EMIR, and PV
- Experience with double pattern finfet required, experience with triple pattern process nodes a plus.
- Proficiency using Perl/Python, TCL, Make scripting.
Other Skills :
- Demonstrates good analysis and problem-solving skills.
- Inherent sense of urgency and accountability.
- Ability to define problems, issues and opportunities, analyze data, establish facts, and draw valid conclusions from various datasets.
- Ability to multi-task in a fast paced environment.
Education : MSEE 8+ years experience or BSEE with 10+ years related experience