Associate consultant at Confidential
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Physical Design Engineer (1-11 yrs)
- Experience in ASIC tape outs, preferably in 28nm, 45nm & 65nm, to leading foundries
- Experience in Block / Chip level P & R.
- Clear understanding and command over all aspects of physical design including technology, libraries, floorplan, timing, signal integrity and power dissipation.
- Skill and efficiency in scripting using Tcl or perl desirable
- Demonstrated ability to work in a team environment
Tools - Synopsys ICC, EDI, PTSI, Calibre/Hercules DRC/LVS
- Implementation of multimillion gate ASIC designs in cutting edge process technologies (28nm, 45nm, 65nm, 90nm)
- Ownership of all aspects of physical design including floor planning, place and route, clock distribution, parasitic extraction, timing closure, power and signal integrity analysis, DFM, and DRC/LVS sign-off.
- Meeting highly challenging schedule, performance, and quality constraints.
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