04/09 Ramya Shree
HR Analyst at Open-Silicon Research Pvt. Ltd.

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Open Silicon Research - DFT Engineer - ATPG/Verification (4-10 yrs)

Bangalore Job Code: 358375

- Complete understanding of DFT concepts and flow (scan/ATPG/Memory BIST/ Bscan, Vtran/Simutest), 


- Should be able to independently handle complete DFT insertions at full chip level,


- Understand IP test requirements, implement/ Verify. 


- Verilog coding for synthesis and testbenches,Test mode timing support/debug and closure at full chip level,


- Handle post-silicon pattern generation, Validation and ATE debug/support,DFT specification creation,


- Complete familiarity/exposure of tools used in DFT implementation (DC/RC, Tk/Tmax, Virage/Mentor memory BIST, Mentor Bscan),


- Should have ability to debug tool /design issues. 


- Low ATPG coverage etc,Familiarity with STA. DFT mode constraints generation. 


- Help STA team in closure for DFT modes,Good scripting skills (TCL/Perl),Debug any issues in implementation and verification and resolve to closure,


- Interact with DM/Lead, STA /PD team to communicate work progress or resolve cross function issues,


- Interact with tool vendors and debug tool related or IP related issues independently.


- Independently debug any issues in implementation and verification and be able to help other team members.


- Provide feedback to FM on problems/issues in flow and help contribute to methodology improvements.Own full chip responsibilities

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