Talent Acquisition at Nexii Labs
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NEXIILABS - Senior STA Engineer - Synthesis/RTL (3-10 yrs)
We have a #IMMEDIATE opening in "SENIOR SYNTHESIS &STA ENGINEER" with our client @Hyderabad
Job Title : STA ENGINEER
- Hands on ownership of Synthesis / Constraints / STA / ECO flow
- Expert in running Block level and Chip level STA in MCMM, DMSA environments
- Must have worked on multiple timing closure and constraint development
- Well versed with AOCV, POCV, Noise fixing methodologies
- Must have worked on ECO implementation cycles - functional, timing
- Interacting with RTL/PD/DFT teams to resolve all implementation issues
- Participate in design reviews and design closure discussions
Job Requirements :
- Good understanding of complete physical design flow.
- Must have gone through multiple tapeout cycles, revisions and ECOs
- Expertise with Synthesis, STA tools (like DC, Primetime) is a must
- Strong scripting skills using Perl, TCL, C-shell, Make and/or other scripting languages.
- Timing characterization and post silicon timing correlation experience a plus.
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