23/05 Apeksha Joshi
Talent Acquisition Specialist at Mirafra technologies

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Mirafra Technologies - RTL Design Engineer - SoC/Verilog (3-10 yrs)

Bangalore Job Code: 447212

JD :


- Verilog/VHDL RTL/Conformal Verification( LEC) Synthesis ( DC )

- Spyglass ( lint, DFT, PM, CLK/RST )

- SoC integration flows ( integrating multiple IPs and associated,

- Understanding of Power Management ( voltage domain, power domains, clock domains )

- OCP and AXI protocols

- ARM understanding

- Misc : Debussy, simulators (mti/ncsim ), Perl

- Ability to Micro- Architect based on feature, performance requirements

- Well versed with design techniques and implement using Verilog/ SystemVerilog

- Ability to analyze Lint, CDC reports from EDA tools

- Good understanding of SDC constraints, Synthesis and STA

- RTL Design for Power/ Area, Implementation from Specification to Netlist

- Responsible for Lint, CDC, timing clean functional netlist

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