19/06 Apeksha Joshi
Talent Acquisition Specialist at Mirafra technologies

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Mirafra Technologies - Physical Design Engineer - RTL/Floor Planning (3-20 yrs)

Bangalore Job Code: 457307

JD :


- Experience in 28nm,14nm and beyond

- Top level implementation, integration and signoff closure

- Low power flow methodologies

- Data Analysis and scripting skills

- Extraction, Static Timing Analysis, SI effects.

- Physical Verification (LVS/DRC/Ant/Density/Reliability checks).

- Multiple Tools exposure

- IR Drop must

- Have in-depth knowledge of entire physical design process from RTL to GDS2 generation which includes floorplan, Placement, CTS, Routing

- Have hands-on experience in latest sub-micron technologies below 20nm

- Have done good number of Block level PnR with Timing Closure

- Familiar with Physical Verification flows (DRC/LVS/EM/IR)

- Experience in ECO implementation

- Hands on experience in leading PnR tools Synopsys ICC/Cadence Encounter etc

- Familiarity with any of Scripting languages PERL, TCL

- Should be a quick learner and have good attention to detail

- Must have good communication & problem-solving skills.

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