15/05 Prince
Staffing Specialist at Mirafra Technologies

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Mirafra - RTL Design Engineer - Verilog/Synopsys (2-10 yrs)

Bangalore Job Code: 444365

RTL Design Engineer

- Knowledge in Verilog/VHDL Expertise in Spyglass Lint/CDC checks and waiver creation

- Expertise in Synopsys Design Compiler Synthesis

- Expertise in formal verification with Cadence LEC

- Good knowledge in gate-level simulation and debugging issues

- Understanding of RTL to GDS flow

- Expertise in Perl, TCL language is a plus.

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