Logic Design/Verification Engineer - SoC/RTL/Timing Closure (8-15 yrs)
Job Title/Designation : Logic Design and Verification Engineer
Job Description :
- Lead position in the Logic Design/Verification team.
- This position requires at least 8 yrs of relevant industry experience.
- Candidate will be involved in the logic design and develop Testbench for the Block / Cluster, Test cases, Test plans and Functional as well as Code coverage.
- Candidate will work on verification of complex SoCs / IPs and provide technical leadership to the team.
- Candidate will develop expertise in multiple areas of verification, RTL, power-aware simulations, drive verification closure, timing closure, formal verification and equivalence checking on complex modules using System Verilog/UVM based methodology.
Skills Required :
- Good understanding of ASIC design, verification concepts, techniques, and process from test plan to coverage completion.
- Prior Experience of verification of complex SoCs / IPs in a leading role in multiple areas of verification, RTL, power-aware simulations, drive verification closure, timing closure, formal verification and equivalence checking on complex modules using System Verilog/UVM based methodology.
- Strong Hands-On experience with Verilog/System Verilog and UVM/OVM/VMM.
- Experience in project planning, resource allocation, scheduling, and status reporting.
- Should be a good mentor and guide for junior engineers in the team.
- Minimum 8 years of experience in Logic Design/Verification.
Minimum/Maximum/ Work Experience Required : 8+ Years
Annual CTC : As per market standards.
Number of Vacancies : 1
Location(s) of Job : Bangalore
Minimum Education Requirements : Bachelors or Masters degree
No of rounds of Interviews : 2
Work Timings : 9:00 AM to 6:00 PM, 5 days a week.
Languages : English
Relocation & Reimbursement : Will be discussed in a face-to-face interview.
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