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13/09 Core Edge
Director at Core Edge Solutions

Views:202 Applications:31 Rec. Actions:Recruiter Actions:18

Logic Design/ASIC Design Engineer - RTL/Verilog/Timing Closure (3-7 yrs)

Bangalore/Trivandrum/Thiruvananthapuram Job Code: 492006

Job Description :

- Develops preSilicon functional validation tests to verify system will meet design requirements.

- Creates test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests. Analyzes and uses results to modify testing.

Qualifications :

- Candidate should have a Master's degree ( M-Tech/ MS) in electrical engineering/ Microelectronics form a reputed institution, with a minimum 3 years of experience.

- Candidate should have good knowledge of digital electronics and understanding of VLSI.

- He / She should have a working knowledge of Verilog/System Verilog and verification methodology.

- He /she should have hands-on experience in writing Test Plans, Coverage, Test cases/Scenarios.

- Working experience on OVM/UVM based methodologies will be advantageous.

- You should have an ASIC design background with hands-on experience in design, verification, physical design, system testing, with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a consistent track record of success in high-performance/high-volume products.

Responsibilities :

- Architectural work : an in-depth understanding of the architecture, and identification of problems and solutions.

- All aspects of implementation : specification, design, verification, timing-closure, power-optimization, and flow automation.

- Physical design work : timing path analysis, optimization of the logic for low power and area; highlighting issues and standard methodologies for power and area optimization.

- Document and improve standard methodologies to make the product successful.

- Lead other specialists in project achievements: schedule, power, area.

- 3+ years up to 15 years of hands on experience in large-scale, high-performance ASICs.

Women-friendly workplace:

Maternity and Paternity Benefits

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