11/04 Bindu
recruitement at alchemytechsol

Views:147 Applications:6 Rec. Actions:Recruiter Actions:6

Lead Verification Engineer - Verilog/System Verilog (15-30 yrs)

Bangalore Job Code: 432361

Here the job description of the Formal verification engineering lead.

Job Description :


External Description Description :


External Responsibilities: 


- Identifying key behaviors for verification of DUT and creating a formal verification plan. 


- Develop and execute a comprehensive FV test plan to verify functionality of the design. 


- Craft the formal verification environment including environment assumptions, assertions and cover properties in context of the formal verification plan. 


- Applying various formal techniques to proof correctness of digital designs. 


- Review formal setups and proofs with design and verification teams. 


- Developing scripts to automate the formal verification process.

Qualifications :


External Minimum Qualifications : 


- Candidate must have BS/MS (preferred) degree in CS/EE or related technical field(s) with 4-10 years of experience. 


Preferred Qualifications : 


- Knowledge/Experience in formal verification techniques. 


- Exposure to industry leading formal verification tools (Jasper, VC Formal, Questa). 


- Understanding of abstraction techniques for effective verification. 


- Working knowledge of HDL/HVL such as Verilog, System Verilog. 


- Hands-on experience with scripting languages (perl/python). 


- Self-motivated team player able to thrive in a fast-paced engineering environment. 


- Demonstrates good analytical and problem-solving skills.

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