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Lead Verification Engineer - ASIC/System Verilog (8-12 yrs)
We believe that the future of Chip making is knowing how they'll perform before they are designed & developed. Our client builds the products that powers this revolution. Our client's platform is delighting the innovative products and we- re looking for creative and passionate Lead Verification Engineer to help lead their Bangalore team.
We'd love to hear from you, if :
- You have 8-12 years of total working experience with good experience in ASIC Verification.
- You have experience in System Verilog.
- You are expertise in UVM/ OVM/ VMM based verification methodology.
- You have the ability to adapt, be creative and learn more.
Responsibilities Required :
- Manage the regressions and analyze functional and code coverage metrics to fill the coverage holes.
- Proactively identifying new methodologies or tools to address an upcoming verification challenges.
- Strong debugging skills of Verilog RTL & test environment is desired
- Experience in planning the verification process and creating realistic schedule estimates.
- Add automation and scripting wherever applicable in the chip design flow.
- Leverage your knowledge of constrained assertion based verification.
Our client is a great place to work, where we know that everyone succeeds together.
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