06/12 Shankar
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Layout Design Lead - ADC/DAC/SERDES (6-8 yrs)

Anywhere in India/Multiple Locations Job Code: 388279

Job Description :

- Primary driver involving feasibility study, specs finalization, project proposal, project management and execution

- Envision, build and lead a team for successful project execution

- Adhere to Project Schedule, Work Assignments and Quality processes

- Strong Customer interface for negotiating specs, design reviews till final sign off

- Mentor and Guide Junior & Senior members of the team

Required Skillset :

- Deep understanding and Managing layout projects of complex Analog and Mixed Signal blocks such as ADC, DAC, Integer & Fractional PLL, Ring Oscillator, LC VCO, CDRs, SerDes, HDMI, Serial I/Os, LVDS, PMIC, DC-DC Buck, Boost & Buck-Boost converters and LDO

- Expertise in High Speed, Low Voltage and Low Power CMOS layout design techniques.

- Exposure to technology node from 0.18um to 10nm, 7nm CMOS/ BiCMOS process

- Good Understanding on signal flow, Clock Routing, Shielding, Load Cap reduction techniques, power & ground structure, Bias signal routing.

- Good debugging skills in all physical verification checks like LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC etc.

- Good knowledge on EMIR and ESD analysis and checks

- Proficiency in using industry standard EDA tools Cadence (Virtuoso-L, Virtuoso-XL, PVS & QRC), Mentor Graphics (Calibre & XRC) and Apache EMIR Analysis.

- Knowledge of scripting and modelling languages like Perl, Skill, Ocean

- Full understanding of hierarchical design planning (top down and bottom up) and integration

- Experience in post-silicon evaluation

- Evaluate new methodology and process improvements to achieve higher efficiency and performance of the team

- Must have multiple tape-outs with silicon success across different processes & foundries

- Experience in RF design is a plus

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