Layout Design Engineer - Verification/CMOS (2-4 yrs)
Job Description :
- Layout design & Verification of high performance Analog & Mixed signal blocks
- Adhere to Project Execution Plan & Work Assignment.
- Support senior members of the team in project planning and implementation.
- Mentor and guide junior members of the team.
Required Skillset :
- Hands on experience in Layout design of basic analog blocks such as Op amps, Comparators, Bandgap, LDOs, Voltage Reference Buffers & Switched capacitor circuits.
- Good Understanding of deep sub-micron layout techniques and issues in CMOS process technology nodes like 7nm, 10nm, 28nm, 45nm, 65nm etc
- Expertise in critical layout design techniques such as Matching, Signal flow, Clock Routing, Shielding, Resistance & Capacitance reduction, Bias and Power routing.
- Debugging skills in physical verification checks like LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC etc.
- Should have good knowledge of CMOS process and fabrication
- Proficiency in using industry standard EDA tools like Cadence (Virtuoso-L, Virtuoso-XL, PVS & QRC), Mentor Graphics (Calibre & XRC)
- Knowledge of scripting languages such as Perl and Skill is a plus.
- Good team player with excellent communication skills.